CDCEL937-Q1

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Automotive catalog programmable 3-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs

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Product details

Parameters

Function Clock generator, Spread-spectrum clock generator Number of outputs 7 Output frequency (Max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type XTAL, LVCMOS Output type LVCMOS Operating temperature range (C) -40 to 125 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Automotive open-in-new Find other Clock generators

Package | Pins | Size

TSSOP (PW) 20 42 mm² 6.5 x 6.4 open-in-new Find other Clock generators

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer Setting
  • Flexible Input Clocking Concept
    • External Crystal: 8 MHz to 32 MHz
    • On-Chip VCXO: Pull Range ±150 ppm
    • Single-Ended LVCMOS up to 160 MHz
  • Free Selectable Output Frequency up to 230  MHz
  • Low-Noise PLL Core
    • Integrated PLL Loop Filter Components
    • Low Period Jitter (Typical 60 ps)
  • Separate Output Supply Pins
    • CDCE937-Q1: 3.3 V and 2.5 V
    • CDCEL937-Q1: 1.8 V
  • Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2]; for Example: SSC Selection, Frequency Switching, Output Enable or Power Down
    • Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth™, WLAN, Ethernet™, and GPS
    • Generates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • 1.8-V Device Power Supply
  • Wide Temperature Range –40°C to 125°C
  • Packaged in TSSOP
  • Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)
  • APPLICATIONS
    • Clusters
    • Head Units
    • Navigation Systems
    • Advanced Driver Assistance Systems (ADAS)

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Description

The CDCE937-Q1 and CDCEL937-Q1 devices are modular, phase-locked loop (PLL) based programmable clock synthesizers. These devices provide flexible and programmable options, such as output clocks, input signals, and control pins, so that the user can configure the CDCEx937-Q1 for their own specifications.

The CDCEx937-Q1 generates up to seven output clocks from a single input frequency to enable both board space and cost savings. Additionally, with multiple outputs, the clock generator can replace multiple crystals with one clock generator. This makes the device well-suited for head unit and telematics applications in infotainment and camera systems in ADAS as these platforms are evolving into smaller and more cost effective systems.

Furthermore, each output can be programmed in-system for any clock frequency up to 230 MHz through the integrated, configurable PLL. The PLL also supports spread-spectrum clocking (SSC) with programmable down and center spread. This provides better electromagnetic interference (EMI) performance to enable customers to pass industry standards such as CISPR-25.

Customization of frequency programming and SSC are accessed using three user-defined control pins. This eliminates the additional interface requirement to control the clock. Specific power-up and power-down sequences can also be defined to the userΩs needs.

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Technical documentation

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Type Title Date
* Data sheet CDCEx937-Q1 Programmable 3-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V LVCMOS Outputs datasheet (Rev. C) Dec. 16, 2016
Technical article How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
Technical article Clocking sampled systems to minimize jitter Jul. 31, 2014
Application note Crystal or Crystal Oscillator Replacement with Silicon Devices Jun. 18, 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014
Application note VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) Apr. 23, 2012
User guide CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) Nov. 22, 2010
Application note General I2C / EEPROM usage for the CDCE(L)9xx family Jan. 26, 2010
Application note Troubleshooting I2C Bus Protocol Oct. 19, 2009
Application note Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Sep. 23, 2009
Application note Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency Mar. 31, 2008

Design & development

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  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
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Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Features
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

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TSSOP (PW) 20 View options

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