CDCM6208V2G

ACTIVE

2:8 Ultra Low Power, Low Jitter Clock Generator, Pin Mode Variant V2G

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Product details

Parameters

Function Ultra-low jitter clock generator Number of outputs 8 Output frequency (Max) (MHz) 800 VCC core (V) 3.3, 2.5, 1.8 VCC out (V) 3.3, 2.5, 1.8 Input type CML, LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, HSDS, LVCMOS, LVDS Operating temperature range (C) -40 to 85 Features I2C, Pin programmable, SPI Rating Catalog open-in-new Find other Clock generators

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other Clock generators

Features

  • Superior Performance with Low Power:
    • Low Noise Synthesizer (265 fs-rms Typical
      Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms
      Typical Jitter)
    • 0.5 W Typical Power Consumption
    • High Channel-to-Channel Isolation and
      Excellent PSRR
    • Device Performance Customizable Through
      Flexible 1.8 V, 2.5 V and 3.3 V Power
      Supplies, Allowing Mixed Output Voltages
  • Flexible Frequency Planning:
    • 4x Integer Down-divided Differential Clock
      Outputs Supporting LVPECL-like, CML, or
      LVDS-like Signaling
    • 4x Fractional or Integer Divided Differential
      Clock Outputs Supporting HCSL, LVDS-like
      Signaling, or Eight CMOS Outputs
    • Fractional Output Divider Achieve 0 ppm to < 1
      ppm Frequency Error and Eliminates need for
      Crystal Oscillators and Other Clock Generators
    • Output frequencies up to 800 MHz
  • Two Differential Inputs, XTAL Support, Ability for
    Smart Switching
  • SPI, I2C™, and Pin Programmable
  • Professional user GUI for Quick Design
    Turnaround
  • 7 × 7 mm 48-QFN package (RGZ)
  • –40 °C to 85 °C temperature range
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Description

The CDCM6208V2G is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V2G also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V2G can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k – 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k – 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency.

In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k – 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V2G is packaged in a small 48-pin 7 mm × 7 mm QFN package.

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Technical documentation

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Type Title Date
* Datasheet CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers datasheet Mar. 07, 2016
Technical articles How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
Technical articles Clocking sampled systems to minimize jitter Jul. 31, 2014
Technical articles Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014

Design & development

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VQFN (RGZ) 48 View options

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