enhanced product general purpose and PCI-X 1:4 clock buffer


Product details


Function Single-ended Additive RMS jitter (Typ) (fs) 56 Output frequency (Max) (MHz) 200 Number of outputs 4 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 150 Features 1:4 fanout Operating temperature range (C) -40 to 105 Rating HiRel Enhanced Product Output type LVTTL Input type LVTTL open-in-new Find other Clock buffers

Package | Pins | Size

TSSOP (PW) 8 19 mm² 3 x 6.4 open-in-new Find other Clock buffers


  • General-Purpose and PCI-X 1:4 Clock Buffer
  • Operating Frequency
    • 0 MHz to 200 MHz General-Purpose
  • Low Output Skew: <100 ps
  • Distributes One Clock Input to One Bank of Four Outputs
  • Output Enable Control that Drives Outputs Low when OE is Low
  • Operates from Single 3.3-V Supply or 2.5-V Supply
  • PCI-X Compliant
  • 8-Pin TSSOP Package
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The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X specifications.

The CDCV304 is characterized for operation from –40°C to 105°C.

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Technical documentation

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Type Title Date
* Data sheet 200-MHz General-Purpose Clock Buffer, PCI-X Compliant datasheet (Rev. A) Mar. 29, 2012
* VID CDCV304-EP VID V6212618 Jun. 21, 2016
* Radiation & reliability report CDCV304TPWREP Reliability Report Aug. 13, 2012

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SCAC024D.ZIP (38 KB) - IBIS Model
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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
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TSSOP (PW) 8 View options

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