CDCVF2505

ACTIVE

PLL Clock Driver for Synch. DRAM & Gen. Purp. Apps W/Spread Spectrum Compatibility, Power Down Mode

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Product details

Parameters

Function Memory interface Output frequency (Max) (MHz) 200 Number of outputs 4 VCC core (V) 3.3 Output skew (ps) 150 Features SDR Operating temperature range (C) -40 to 85 Rating Catalog Output type LVCMOS open-in-new Find other Clock buffers

Package | Pins | Size

SOIC (D) 8 19 mm² 3.91 x 4.9 TSSOP (PW) 8 19 mm² 3 x 6.4 open-in-new Find other Clock buffers

Features

  • Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 24 MHz to 200 MHz
  • Low Jitter (Cycle-to-Cycle): < |150 ps| (Over 66 MHz to 200 MHz Range)
  • Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Used to Tune the Input-Output Delay)
  • Three-States Outputs When There Is No Input Clock
  • Operates From Single 3.3-V Supply
  • Available in 8-Pin TSSOP and 8-Pin SOIC Packages
  • Consumes Less Than 100 mA (Typical) in Power-Down Mode
  • Internal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock
  • 25-Ω On-Chip Series Damping Resistors
  • Integrated RC PLL Loop Filter Eliminates the Need for External Components
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Description

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN.

The loop filter for the PLLs is included on-chip. This minimizes the component count, space, and cost.

The CDCVF2505 is characterized for operation from –40°C to 85°C.

Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

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Technical documentation

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Type Title Date
* Datasheet CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver datasheet (Rev. G) Aug. 31, 2016
Selection guides Clock & Timing Solutions (Rev. C) Jan. 19, 2017
Application notes Design and Layout Guidelines for the CDCVF2505 Clock Driver (Rev. A) Mar. 07, 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODELS Download
SCAC027B.ZIP (15 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SOIC (D) 8 View options
TSSOP (PW) 8 View options

Ordering & quality

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