CY74FCT245T

ACTIVE

Octal Bus Transceivers with 3-State Outputs

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Product details

Parameters

Technology Family FCT VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Bits (#) 8 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 70 ICC @ nom voltage (Max) (mA) 0.2 Propagation delay (Max) (ns) 7 IOL (Max) (mA) 64 IOH (Max) (mA) -32 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Standard transceiver

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SSOP (DBQ) 20 52 mm² 8.65 x 6 open-in-new Find other Standard transceiver

Features

  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • CY54FCT245T
    • 48-mA Output Sink Current
      12-mA Output Source Current
  • CY74FCT245T
    • 64-mA Output Sink Current
      32-mA Output Source Current
  • 3-State Outputs

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Description

The \x92FCT245T devices contain eight noninverting bidirectional buffers with 3-state outputs and are intended for bus-oriented applications.

The transmit/receive (T/R\) input determines the direction of data flow through these bidirectional transceivers. Transmit (active high) enables data from A ports to B ports. The output enable (OE\), when high, disables both the A and B ports by putting them in the high-impedance state.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet 8-Bit Transceivers With 3-State Outputs datasheet (Rev. B) Nov. 02, 2001
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides CYFCT Parameter Measurement Information Apr. 02, 2001
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCCM001.ZIP (8 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SOIC (DW) 20 View options
SSOP (DBQ) 20 View options

Ordering & quality

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