DAC2900

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Dual-Channel, 10-Bit, 125-MSPS Digital-to-Analog Converter (DAC)

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Product details

Parameters

Resolution (Bits) 10 Number of DAC channels (#) 2 Interface type Parallel CMOS Sample/update rate (MSPS) 125 Features Low Power Rating Catalog Interpolation 1x Power consumption (Typ) (mW) 310 SFDR (dB) 80 Operating temperature range (C) -40 to 85 open-in-new Find other High-speed DACs (>10MSPS)

Package | Pins | Size

TQFP (PFB) 48 81 mm² 9 x 9 open-in-new Find other High-speed DACs (>10MSPS)

Features

  • 125MSPS UPDATE RATE
  • SINGLE SUPPLY: +3.3V or +5V
  • HIGH SFDR: 68dB at fOUT = 20MHz
  • LOW GLITCH: 2pVs
  • LOW POWER: 310mW at +5V
  • INTERNAL REFERENCE
  • POWER-DOWN MODE: 23mW
  • APPLICATIONS
    • COMMUNICATIONS:
          Base Stations, WLL, WLAN
          Baseband I/Q Modulation
    • MEDICAL/TEST INSTRUMENTATION
    • ARBITRARY WAVEFORM GENERATORS (ARB)
    • DIRECT DIGITAL SYNTHESIS (DDS)

open-in-new Find other High-speed DACs (>10MSPS)

Description

The DAC2900 is a monolithic, 10-bit, dual-channel, high-speed Digital-to-Analog Converter (DAC), and is optimized to provide high dynamic performance while dissipating only 310mW on a +5V single supply.

Operating with high update rates of up to 125MSPS, the DAC2900 offers exceptional dynamic performance, and enables the generation of very-high output frequencies suitable for "Direct IF" applications. The DAC2900 has been optimized for communications applications in which separate I and Q data are processed while maintaining tight gain-and offset matching.

Each DAC has a high-impedance differential-current output, suitable for single-ended or differential analog-output configurations.

The DAC2900 combines high dynamic performance with a high throughput rate to create a cost-effective solution for a wide variety of waveform-synthesis applications:

  • Pin compatibility between family members provides 10-bit (DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904) resolution.
  • Pin compatible to the AD9763 dual DAC.
  • Gain matching is typically 0.5% of full-scale, and offset matching is specified at 0.02% max.
  • The DAC2900 utilizes an advanced CMOS process; the segmented architecture minimizes output-glitch energy, and maximizes the dynamic performance.
  • All digital inputs are +3.3V and +5V logic compatible. The DAC2900 has an internal reference circuit, and allows use of an external reference.
  • The DAC2900 is available in a TQFP-48 package, and is specified over the extended industrial temperature range of –40°C to +85°C.
open-in-new Find other High-speed DACs (>10MSPS)
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Technical documentation

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Type Title Date
* Datasheet Dual, 10-Bit ,125MSPS Digital-to-Analog Converter datasheet (Rev. C) Sep. 19, 2008
Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
Technical article Digital signal processing in RF sampling DACs – part 2 Apr. 04, 2017
Technical article Digital signal processing in RF sampling DACs - part 1 Feb. 13, 2017
Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note Wideband Complementary Current Output DAC Single-Ended Interface (Rev. A) May 08, 2015
User guide DAC290x-EVM: Demo Board (Rev. B) Sep. 20, 2005

Design & development

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TQFP (PFB) 48 View options

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