DAC5675A

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14-Bit, 400-MSPS Digital-to-Analog Converter (DAC)

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Product details

Parameters

Resolution (Bits) 14 Number of DAC channels (#) 1 Interface type Parallel LVDS Sample/update rate (MSPS) 400 Features High Performance Rating Catalog Interpolation 1x Power consumption (Typ) (mW) 660 SFDR (dB) 88 Architecture Current Sink Operating temperature range (C) -40 to 85 Reference type Int open-in-new Find other High-speed DACs (>10MSPS)

Package | Pins | Size

HTQFP (PHP) 48 49 mm² 7 x 7 open-in-new Find other High-speed DACs (>10MSPS)

Features

  • 400MSPS Update Rate
  • LVDS-Compatible Input Interface
  • Spurious-Free Dynamic Range (SFDR) to Nyquist:
    • 69dBc at 70MHz IF, 400MSPS
  • W-CDMA Adjacent Channel Power Ratio (ACPR):
    • 73dBc at 30.72MHz IF, 122.88MSPS
    • 71dBc at 61.44MHz IF, 245.76MSPS
  • Differential Scalable Current Sink Outputs: 2mA to 20mA
  • On-Chip 1.2V Reference
  • Single 3.3V Supply Operation
  • Power Dissipation: 660mW at fCLK = 400MSPS, fOUT = 20MHz
  • Package: 48-Pin HTQFP PowerPad,
    TJA = 28.8°C/W
open-in-new Find other High-speed DACs (>10MSPS)

Description

The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter. The DAC5675A is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes the DAC5675A well-suited for multicarrier transmission in TDMA- and CDMA-based cellular base transceiver stations (BTSs).

The DAC5675A operates from a single-supply voltage of 3.3 V. Power dissipation is 660 mW at fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675A provides a nominal full-scale differential current output of 20mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD.

The DAC5675A comprises a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference (EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The DAC5675A current-sink-array architecture supports update rates of up to 400MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing.

The DAC5675A has been specifically designed for a differential transformer-coupled output with a 50 Ω doubly- terminated load. With the 20 mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) are supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD –1 to AVDD + 0.3 V.

An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied. The DAC5675A features a SLEEP mode, which reduces the standby power to approximately 18 mW.

The DAC5675A is available in a 48-pin HTQFP thermally-enhanced PowerPad package. This package increases thermal efficiency in a standard size IC package. The device is characterized for operation over the industrial temperature range of –40°C to +85°C.

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Technical documentation

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Type Title Date
* Data sheet DAC5675A 14-Bit, 400-MSPS Digital-to-Analog Converter datasheet (Rev. D) Jul. 01, 2016
Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
Application note Q3 2009 Issue Analog Applications Journal Sep. 24, 2018
Technical article Digital signal processing in RF sampling DACs – part 2 Apr. 04, 2017
Technical article Digital signal processing in RF sampling DACs - part 1 Feb. 13, 2017
Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note Design for a Wideband Differential Transimpedance DAC Output (Rev. A) Oct. 17, 2016
Application note Wideband Complementary Current Output DAC Single-Ended Interface (Rev. A) May 08, 2015
Application note High Speed, Digital-to-Analog Converters Basics (Rev. A) Oct. 23, 2012
Application note Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs Jul. 14, 2009
Application note Passive Terminations for Current Output DACs Nov. 10, 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008
Application note Design for a Wideband Differential Transimpedance DAC Output Apr. 18, 2008
User guide DAC5675 Evaluation Module User's Guide (Rev. A) Mar. 30, 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
199
Description

The DAC5675A EVM provides a platform for evaluating the DAC5675A, 14-bit 400MSPS digital to analog converters (DAC) family under various signal reference, and supply conditions.

Features
  • Provides analog output via SMA connectors.
  • Ease of use and evaluation.
  • External DAC reference option.

Design tools & simulation

SIMULATION MODEL Download
SLAM016A.ZIP (4 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
CALCULATION TOOL Download

CAD/CAE symbols

Package Pins Download
HTQFP (PHP) 48 View options

Ordering & quality

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  • Ongoing reliability monitoring

Support & training

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