The DS90CF386 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CF366 receiver that converts three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the falling edge. A rising edge or falling edge strobe transmitter will interoperate with a falling edge strobe receiver without any translation logic.
The receiver LVDS clock operates at rates from 20 MHz to 85 MHz. The device phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 85 MHz, each LVDS input line is running at a bit rate of 595 Mbps, resulting in a maximum throughput of 2.38 Gbps for the DS90CF386 and 1.785 Gbps for the DS90CF366.
The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high-speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages. The DS90CF386 is also offered in a 64-pin, 0.8-mm, fine pitch ball grid array (NFBGA) package which provides a 44% reduction in PCB footprint compared to the 56-pin TSSOP package.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz datasheet (Rev. J) | PDF | HTML | May 31, 2016 |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | Nov 9, 2018 | ||
| Application note | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | Jun 29, 2018 | ||
| Application note | AN-1032 An Introduction to FPD-Link (Rev. C) | Aug 8, 2017 | ||
| User guide | FLINK3V8BT-85 Evaluation Kit (Rev. A) | Aug 24, 2016 | ||
| Application note | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | Jan 13, 2016 | |
| Application note | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | May 15, 2004 | ||
| Application note | AN-1056 STN Application Using FPD-Link | May 14, 2004 | ||
| Application note | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | May 14, 2004 |
For additional terms or required resources, click any title below to view the detail page where available.
The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
| NFBGA (NZC) | 64 | Ultra Librarian |
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.