DS92LV16

ACTIVE

16-bit bus LVDS serializer/deserializer - 25 - 80 MHz

Product details

Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 2560 Input signal BLVDS, LVDS, LVTTL Output signal BLVDS, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 2560 Input signal BLVDS, LVDS, LVTTL Output signal BLVDS, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PN) 80 196 mm² (14 mm × 14 mm)
  • 25–80 MHz 16:1/1:16 Serializer/Deserializer (2.56Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation With Separate Clock, Enable, Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks To Random Data)
  • Wide +/−5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 104mA (typ) Transmitter, 119mA (typ) Receiver at 80MHz
  • ±100mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.5kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

  • 25–80 MHz 16:1/1:16 Serializer/Deserializer (2.56Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation With Separate Clock, Enable, Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks To Random Data)
  • Wide +/−5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 104mA (typ) Transmitter, 119mA (typ) Receiver at 80MHz
  • ±100mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.5kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit, or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback.

The DS92LV16 incorporates BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit, or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback.

The DS92LV16 incorporates BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Similar functionality to the compared device.
DS92LV18 ACTIVE 18-bit bus LVDS serializer/deserializer - 15-66 MHz Lower speed (2376Mbps)

Technical documentation

No results found. Please clear your search and try again.
View all 7
Top documentation Type Title Format options Date
* Data sheet DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz datasheet (Rev. H) Apr 16, 2013
Application note DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) Apr 29, 2013
Application note DS92LV16 Power Up Reset (Rev. B) Apr 26, 2013
Application note How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A) Apr 26, 2013
Application note External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) Apr 26, 2013
Design guide DS92LV16 16-bit SerDes Design Guide Mar 29, 2007
White paper Easy-to-Use LVDS Serdes for the Serdes Neophyte Sep 1, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

DS92LV16 IBIS Model

SNLM027.ZIP (18 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
LQFP (PN) 80 Ultra Librarian

Ordering & quality

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos