Top

Product details

Parameters

Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 2376 Input signal LVTTL, BLVDS Output signal LVDS, BLVDS, LVTTL Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

LQFP (PN) 80 196 mm² 14 x 14 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)
  • Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern
  • ±100 mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.0kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

open-in-new Find other LVDS, M-LVDS & PECL ICs

Description

The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.

The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

open-in-new Find other LVDS, M-LVDS & PECL ICs
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 5
Type Title Date
* Datasheet DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz datasheet (Rev. E) Apr. 18, 2013
Application notes DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) Apr. 29, 2013
Application notes External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) Apr. 26, 2013
User guides 18-Bit SerDes Evaluation Kit User Manual Jan. 25, 2012
User guides 18-bit SerDes Design Guide (DS92LV18, SCAN921821) Mar. 29, 2007

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
399
Description

The LVDS-18B-EVK evaluation kit (EVK) is a complete kit to evaluate our 18-bit SerDes devices (DS92LV18 and SCAN921821) with low-cost twisted pair cables and other 100-Ω differential cables.

Design tools & simulation

SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOLS Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
LQFP (PN) 80 View options

Ordering & quality

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos