Jitter cleaner with integrated 1840 to 2160-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS


Product details


Function Cascaded PLLs Number of outputs 6 RMS jitter (fs) 160 Output frequency (Min) (MHz) 0.45 Output frequency (Max) (MHz) 2160 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVDS, LVPECL Supply voltage (Min) (V) 3.15 Supply voltage (Max) (V) 3.45 Features Loss of signal detection Operating temperature range (C) -40 to 85 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

WQFN (RHS) 48 49 mm² 7 x 7 open-in-new Find other Clock jitter cleaners & synchronizers


  • Cascaded PLLatinum PLL Architecture
    • PLL1Redundant Reference Inputs Loss of Signal
      DetectionAutomatic and Manual Selection of
      Reference Clock Input
    • PLL2Phase Detector Rate up to 100 MHzInput
      Frequency-DoublerIntegrated VCO
  • Outputs
    • LVPECL/2VPECL, LVDS, and
      LVCMOS Formats
    • Support Clock Rates up to 1080 MHz
    • Five Dedicated Channel Divider Blocks
    • Common Output Frequencies Supported:
      30.72 MHz, 61.44 MHz, 62.5 MHz,
      74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz,
      106.25 MHz, 125 MHz, 122.88 MHz,
      150 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz,
      187.5 MHz, 200 MHz,
      212.5 MHz, 245.76 MHz, 250 MHz, 311.04 MHz,
      312.5 MHz, 368.64 MHz,
      491.52 MHz, 622.08 MHz, 625 MHz, 983.04 MHz
  • MICROWIRE (SPI) Programming Interface
  • Industrial Temperature Range: –40 to 85 °C
  • 3.15 V to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 × 7.0 × 0.8 mm)
open-in-new Find other Clock jitter cleaners & synchronizers


The LMK04100 family of precision clock conditioners provides jitter cleaning, clock multiplication and distribution without the need for high-performance VCXO modules.

When connected to a recovered system reference clock and a VCXO, the device generates 5 low jitter clocks in LVCMOS, LVDS, or LVPECL formats.

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Technical documentation

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Type Title Date
* Data sheet LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs datasheet (Rev. B) Feb. 17, 2013
User guide LMK041xx Family Evaluation Board Operating Instructions (Rev. B) Aug. 16, 2017
Application note AN-1910 LMK04000 Family Phase Noise Characterization (Rev. A) Apr. 26, 2013
Application note AN-1939 Crystal Based Oscillator Design with the LMK04000 Family (Rev. A) Apr. 26, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

Software development

Clock Design Tool - Loop Filter & Device Configuration + Simulation
CLOCKDESIGNTOOL The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
  • Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
  • Export programming configurations for use in end application.
CodeLoader Software for device register programming
CODELOADER The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

Which software do I use?


Loop (...)

Design tools & simulation

SNAM105A.ZIP (71 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

CAD/CAE symbols

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WQFN (RHS) 48 View options

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