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LMK1D1208P

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8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer with pin control

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Data sheet

LMK1D1208P

ACTIVE
Data sheet Order now

Product details

Function Clock buffer, Differential Additive RMS jitter (typ) (fs) 50 Output frequency (max) (MHz) 2000 Number of outputs 8 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features 2:8 fanout, Individual output enable control, Pin control, Universal inputs Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Function Clock buffer, Differential Additive RMS jitter (typ) (fs) 50 Output frequency (max) (MHz) 2000 Number of outputs 8 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features 2:8 fanout, Individual output enable control, Pin control, Universal inputs Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
VQFN (RHA) 40 36 mm² 6 x 6
  • High-performance LVDS clock buffer family with 2 inputs and 8 outputs (2:8)
  • Output frequency up to 2 GHz
  • Hardware pins for individual output enable/disable
  • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
  • Low additive jitter: < 60 fs rms maximum in 12 kHz to 20 MHz at 156.25 MHz

    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • Fail-safe inputs
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
  • LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:
    • 6-mm × 6-mm, 40-pin VQFN (RHA)
  • High-performance LVDS clock buffer family with 2 inputs and 8 outputs (2:8)
  • Output frequency up to 2 GHz
  • Hardware pins for individual output enable/disable
  • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
  • Low additive jitter: < 60 fs rms maximum in 12 kHz to 20 MHz at 156.25 MHz

    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • Fail-safe inputs
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
  • LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:
    • 6-mm × 6-mm, 40-pin VQFN (RHA)

The LMK1D1208P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1208P is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high 1. If this pin is set to a logic low 0, the output is disabled in a Hi-Z state resulting in reduced power consumption.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D1208P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1208P is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high 1. If this pin is set to a logic low 0, the output is disabled in a Hi-Z state resulting in reduced power consumption.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
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* Data sheet LMK1D1208P Pin-Controlled OE Low Additive Jitter LVDS Buffer datasheet (Rev. A) PDF | HTML 02 Jun 2023

Design & development

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Evaluation board

LMK1D1212EVM — LMK1D1212 low jitter 2:12 LVDS fan-out buffer evaluation module

LMK1D1212 is a high-performance, low additive jitter LVDS clock buffer with two differential inputs and 12 LVDS outputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1D1212. This EVM can also be used to evaluate other 40 pin devices in the LMK1Dxxxx (...)
User guide: PDF | HTML
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Simulation model

LMK1DX IBIS Model (Rev. A)

SNAM251A.ZIP (55 KB) - IBIS Model
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Design tool

PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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Supported products & hardware

Supported products & hardware

Products
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Clock jitter cleaners & synchronizers
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Clock buffers
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Clock generators
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IQ demodulators
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Hardware development
Evaluation board
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Software
Application software & framework
PLLATINUMSIM-SW — Texas Instruments PLLatinum Simulator Tool TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software
IDE, configuration, compiler or debugger
CODELOADER — CodeLoader Software for device register programming LMX9830-SW — LMX9830 Application Notes, Software, and Tools LMX9838-SW — LMX9838 Application Notes, Software, and Tools
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Simulation tool

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VQFN (RHA) 40 View options
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