Military grade C80x fixed point DSP


Product details


DSP 1 C2x DSP MHz (Max) 50 CPU 32-bit Rating Catalog Operating temperature range (C) -55 to 125 open-in-new Find other Digital signal processors (DSPs)

Package | Pins | Size

CFP (HFH) 320 58 mm² 44 x 44 CPGA (GF) 305 2233 mm² 47.2 x 47.2 open-in-new Find other Digital signal processors (DSPs)


  • Single-Chip Parallel Multiple Instruction/Multiple Data (MIMD) Digital Signal Processor (DSP)
  • More Than Two Billion RISC-Equivalent Operations per Second
  • Master Processor (MP)
    • 32-Bit Reduced Instruction Set Computing (RISC) Processor
    • IEEE-754 Floating-Point Capability
    • 4K-Byte Instruction Cache
    • 4K-Byte Data Cache
  • Four Parallel Processors (PP)
    • 32-Bit Advanced DSPs
    • 64-Bit Opcode Provides Many Parallel Operations per Cycle
    • 2K-Byte Instruction Cache and 8K-Byte Data RAM per PP
  • Transfer Controller (TC)
    • 64-Bit Data Transfers
    • Up to 400 Megabytes per Second (MBps) Transfer Rate
    • 32-Bit Addressing
    • Direct DRAM/VRAM Interface With Dynamic Bus Sizing
    • Intelligent Queuing and Cycle Prioritization
  • Video Controller (VC)
    • Provides Video Timing and Video Random-Access Memory (VRAM) Control
    • Dual-Frame Timers for Two Simultaneous Image-Capture and/or Display Systems
  • Big- or Little-Endian Operation
  • 50K-Byte On-Chip RAM
  • 4G-Byte Address Space
  • 20-ns Cycle Time
  • 3.3-V Operation
  • IEEE Standard 1149.1 Test Access Port (JTAG)
  • Operating Temperature Range
       –55°C to 125°C - M-Temperature
       –40°C to 85°C - A-Temperature

IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture

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The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly through an on-chip crossbar that provides shared access to on-chip RAM. This performance and programmability make the ’C80 ideally suited for video, imaging, and high-speed telecommunications applications.

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Technical documentation

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* Data sheet SMJ320C80 Digital Signal Processor datasheet (Rev. B) Jun. 30, 2002
Technical article Bringing the next evolution of machine learning to the edge Nov. 27, 2018
Technical article Industry 4.0 spelled backward makes no sense – and neither does the fact that you haven’t heard of TI’s newest processor yet Oct. 30, 2018
Technical article How quality assurance on the Processor SDK can improve software scalability Aug. 22, 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors Jul. 21, 2016
More literature SM320C80/SMJ320C80 (Rev. C) Aug. 07, 2000
User guide TMS320C8x Emulator Installation Guide (Rev. A) Feb. 01, 1997
Application note Modified Goertzel Algorithm in DTMF Detection Using the TMS320C80 DSP Jun. 01, 1996
Application note Acoustic Echo Cancellation Algorithms and Implementation on the TMS320C80 May 01, 1996
User guide TMS320C80 to TMS320C82 Software Compatibility User's Guide Nov. 01, 1995
Application note TMS320C8x System-Level Synopsis (Rev. B) Sep. 01, 1995
User guide TMS320C8x (MVP) Video Controller User's Guide (Rev. A) Jan. 01, 1995

Design & development

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Design tools & simulation

SGUM006.ZIP (7 KB) - BSDL Model
Arm-based MPU, arm-based MCU and DSP third-party search tool
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CFP (HFH) 320 View options
CPGA (GF) 305 View options

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