SM320C80

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Digital Signal Processors

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Product details

Parameters

Cycle time (ns) 20 Data/program memory space (words) 2.4G DMA (Ch) 1 MIPS 60 MOPS 120 Operating temperature range (C) -55 to 125 Rating Military open-in-new Find other Other DSPs

Package | Pins | Size

CFP (HFH) 320 CFP (HFH) 320 CPGA (GF) 305 open-in-new Find other Other DSPs

Features

  • Single-Chip Parallel Multiple Instruction/Multiple Data (MIMD) Digital Signal Processor (DSP)
  • More Than Two Billion RISC-Equivalent Operations per Second
  • Master Processor (MP)
    • 32-Bit Reduced Instruction Set Computing (RISC) Processor
    • IEEE-754 Floating-Point Capability
    • 4K-Byte Instruction Cache
    • 4K-Byte Data Cache
  • Four Parallel Processors (PP)
    • 32-Bit Advanced DSPs
    • 64-Bit Opcode Provides Many Parallel Operations per Cycle
    • 2K-Byte Instruction Cache and 8K-Byte Data RAM per PP
  • Transfer Controller (TC)
    • 64-Bit Data Transfers
    • Up to 400 Megabytes per Second (MBps) Transfer Rate
    • 32-Bit Addressing
    • Direct DRAM/VRAM Interface With Dynamic Bus Sizing
    • Intelligent Queuing and Cycle Prioritization
  • Video Controller (VC)
    • Provides Video Timing and Video Random-Access Memory (VRAM) Control
    • Dual-Frame Timers for Two Simultaneous Image-Capture and/or Display Systems
  • Big- or Little-Endian Operation
  • 50K-Byte On-Chip RAM
  • 4G-Byte Address Space
  • 20-ns Cycle Time
  • 3.3-V Operation
  • IEEE Standard 1149.1 Test Access Port (JTAG)
  • Operating Temperature Range
       –55°C to 125°C - M-Temperature
       –40°C to 85°C - A-Temperature

IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture

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Description

The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly through an on-chip crossbar that provides shared access to on-chip RAM. This performance and programmability make the ’C80 ideally suited for video, imaging, and high-speed telecommunications applications.

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Technical documentation

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Type Title Date
* Datasheet SMJ320C80 Digital Signal Processor datasheet (Rev. B) Jun. 30, 2002
More literature SM320C80/SMJ320C80 (Rev. C) Aug. 07, 2000
User guides TMS320C8x Emulator Installation Guide (Rev. A) Feb. 01, 1997
Application notes Modified Goertzel Algorithm in DTMF Detection Using the TMS320C80 DSP Jun. 01, 1996
Application notes Acoustic Echo Cancellation Algorithms and Implementation on the TMS320C80 May 01, 1996
User guides TMS320C80 to TMS320C82 Software Compatibility User's Guide Nov. 01, 1995
Application notes TMS320C8x System-Level Synopsis (Rev. B) Sep. 01, 1995
User guides TMS320C8x (MVP) Video Controller User's Guide (Rev. A) Jan. 01, 1995

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODELS Download
SGUM006.ZIP (7 KB) - BSDL Model

CAD/CAE symbols

Package Pins Download
CFP (HFH) 320 View options
CPGA (GF) 305 View options

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