Product details

Technology Family AC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 100 Rating Space
Technology Family AC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 100 Rating Space
CDIP (J) 14 130 mm² 19.94 x 6.73 CFP (W) 14 55 mm² 9.2 x 6.39
  • 5962R87549:
    • Radiation hardness assurance (RHA) up to TID 100 krad (Si)
    • SEL immune to 86 MeV×cm2/mg
  • 5962-87549:
    • Total ionizing dose 50 krad (Si)
  • 2 V to 6 V VCC operation
  • Inputs accept voltages to 6 V
  • Maximum tpd of 7 ns at 5 V
  • 5962R87549:
    • Radiation hardness assurance (RHA) up to TID 100 krad (Si)
    • SEL immune to 86 MeV×cm2/mg
  • 5962-87549:
    • Total ionizing dose 50 krad (Si)
  • 2 V to 6 V VCC operation
  • Inputs accept voltages to 6 V
  • Maximum tpd of 7 ns at 5 V

The SN54AC00 device contains four independent 2-input NAND gates. Each gate performs the Boolean function of Y = A • B or Y = A + B in positive logic.

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The SN54AC00 device contains four independent 2-input NAND gates. Each gate performs the Boolean function of Y = A • B or Y = A + B in positive logic.

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Technical documentation

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Type Title Date
* Data sheet SN54AC00-SP Radiation Hardened Quad 2 Input NAND Gate datasheet (Rev. C) PDF | HTML 04 Apr 2022
* SMD SN54AC00-SP SMD 5962-87549 08 Jul 2016
* Radiation & reliability report 54AC00-SP Radiation Assured Devices 21 Apr 2016
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 17 Nov 2022
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19 Oct 2022
Selection guide TI Space Products (Rev. I) 03 Mar 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing 17 Jun 2019
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
White paper 54AC00-SP 50-krad TID Report 26 Mar 2015
More literature HiRel Unitrode Power Management Brochure 07 Jul 2009
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

SN54AC00 IBIS Model

SCHM007.ZIP (22 KB) - IBIS Model
Package Pins Download
(KGD) 0 View options
CDIP (J) 14 View options
CFP (W) 14 View options

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