SN64BCT125A

ACTIVE

Quadruple Bus Buffer Gate With 3-State Outputs

Top

Product details

Parameters

Technology Family BCT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 4 IOL (Max) (mA) 64 ICC (Max) (uA) 49000 IOH (Max) (mA) -15 Input type TTL-Compatible CMOS Output type 3-State Features Very high speed (tpd 5-10ns), Power up 3-state Data rate (Mbps) 140 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other Non-Inverting buffer/driver

Features

  • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
  • High-Impedance State During Power-Up and Power-Down
  • 3-State Outputs Drive Bus Lines or Buffer-Memory Address Registers
  • ESD Protection Exceeds 2000 V Per MIL-STD-883C Method 3015
  • Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)

 

open-in-new Find other Non-Inverting buffer/driver

Description

The SN64BCT125A bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable () input is high.

The SN64BCT125A is characterized for operation from -40°C to 85°C and 0°C to 70°C.

open-in-new Find other Non-Inverting buffer/driver
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 12
Type Title Date
* Datasheet Quadruple Bus Buffer Gate With 3-State Outputs datasheet (Rev. B) May 01, 1994
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCBM099.ZIP (9 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos