SN65EPT21

ACTIVE

3.3-V ecl differential receiver

Product details

Function Receiver, Translator Protocols LVDS, PECL Number of transmitters 0 Number of receivers 1 Signaling rate (Mbps) 600 Input signal LVDS, PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver, Translator Protocols LVDS, PECL Number of transmitters 0 Number of receivers 1 Signaling rate (Mbps) 600 Input signal LVDS, PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) VSSOP (DGK) 8 14.7 mm² (3 mm × 4.9 mm)
  • 1 ns Propagation Delay
  • Fmax > 300MHz
  • Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
  • 24-mA TTL Output
  • Built-In Temperature Compensation
  • Drop-In Compatible to the MC10EPT21, MC100EPT21
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data
  • 1 ns Propagation Delay
  • Fmax > 300MHz
  • Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
  • 24-mA TTL Output
  • Built-In Temperature Compensation
  • Drop-In Compatible to the MC10EPT21, MC100EPT21
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data

The SN65EPT21 is a differential PECL-to-TTL translator. It operates on +3.3 V supply and ground only. The device includes circuitry to maintain inputs at Vcc/2 when left open.

The VBB pin is a reference voltage output for the device. When the device is used in single-ended mode, the unused input should be tied to VBB. This reference voltage can also be used to bias the input when it is ac coupled. When it is used, place a 0.01µF decoupling capacitor between VCC and VBB. Also limit the sink/source current to < 0.5 mA to VBB. Leave VBB open when it is not used.

The SN65EPT21 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.

The SN65EPT21 is a differential PECL-to-TTL translator. It operates on +3.3 V supply and ground only. The device includes circuitry to maintain inputs at Vcc/2 when left open.

The VBB pin is a reference voltage output for the device. When the device is used in single-ended mode, the unused input should be tied to VBB. This reference voltage can also be used to bias the input when it is ac coupled. When it is used, place a 0.01µF decoupling capacitor between VCC and VBB. Also limit the sink/source current to < 0.5 mA to VBB. Leave VBB open when it is not used.

The SN65EPT21 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet 3.3V ECL Differential Receiver datasheet Feb 10, 2009
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct 17, 2007

Design & development

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Simulation model

SN65EPT21 IBIS Model

SLLM145.ZIP (16 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian

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