SN65MLVD3

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1-channel M-LVDS Type-2 receiver

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Data sheet

document-pdfAcrobat Single M-LVDS Receivers datasheet

SN65MLVD3

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Data sheet

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Product details

Function

Receiver

Protocols

M-LVDS

Number of transmitters

0

Number of receivers

1

Signaling rate (Mbps)

250

Input signal

M-LVDS

Output signal

LVTTL

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Function

Receiver

Protocols

M-LVDS

Number of transmitters

0

Number of receivers

1

Signaling rate (Mbps)

250

Input signal

M-LVDS

Output signal

LVTTL

Rating

Catalog

Operating temperature range (°C)

-40 to 85

VSON (DRB)

8

9 mm² (3 mm × 3 mm)

Low-Voltage Differential 30- Line Receivers for Signaling Rates⁽¹⁾ up to 250Mbps; Clock Frequencies up to 125MHz
SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis
SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions
Wide Receiver Input Common-Mode Voltage Range, -1 V to 3.4 V, Allows 2 V of Ground Noise
Improved V_IT (35 mV)
Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Topology
High Input Impedance with Low Supply Voltage
Bus-Pin HBM ESD Protection Exceeds 9 kV
Packaged in 8-Pin SON (DRB) 70% Smaller Than 8-Pin SOIC
APPLICATIONS
- Parallel Multipoint Data and Clock Transmission via Backplanes and Cables
- Cellular Base Stations
- Central Office Switches
- Network Switches and Routers

⁽¹⁾ The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second).

Low-Voltage Differential 30- Line Receivers for Signaling Rates⁽¹⁾ up to 250Mbps; Clock Frequencies up to 125MHz
SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis
SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions
Wide Receiver Input Common-Mode Voltage Range, -1 V to 3.4 V, Allows 2 V of Ground Noise
Improved V_IT (35 mV)
Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Topology
High Input Impedance with Low Supply Voltage
Bus-Pin HBM ESD Protection Exceeds 9 kV
Packaged in 8-Pin SON (DRB) 70% Smaller Than 8-Pin SOIC
APPLICATIONS
- Parallel Multipoint Data and Clock Transmission via Backplanes and Cables
- Cellular Base Stations
- Central Office Switches
- Network Switches and Routers

⁽¹⁾ The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second).

The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled.

The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD2) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers (SN65MLVD3) implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.

The devices are characterized for operation from -40°C to 85°C.

The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled.

The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD2) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers (SN65MLVD3) implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.

The devices are characterized for operation from -40°C to 85°C.

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Technical documentation

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Top documentation	Type	Title	Format options	Date
*	Data sheet	Single M-LVDS Receivers datasheet		Nov 2, 2006
	Application note	An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C)	PDF \| HTML	Jun 22, 2023
	Application brief	How Far, How Fast Can You Operate MLVDS?		Aug 6, 2018
	Application note	SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A)		Nov 20, 2001

Design & development

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Evaluation board

SN65MLVD2-3EVM — SN65MLVD2-3EVM Evaluation Module

The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to250 Mbps. Each receiver channel is controlled by a receive enable (/RE). When /RE = low, (...)

User guide: PDF

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Simulation model