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Product details

Parameters

Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 8 19 mm² 3.91 x 4.9 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • Low-Voltage Differential 30- Line Drivers and Receivers for Signaling Rates(1) Up to 200 Mbps
  • Type-1 Receivers Incorporate 25 mV of Hysteresis
  • Type-2 Receivers Provide an Offset (100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions
  • Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • –1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise
  • Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V
  • 100-Mbps Devices Available (SN65MLVD200A, 202A, 204A, 205A)
  • M-LVDS Bus Power Up/Down Glitch Free
  • APPLICATIONS
    • Low-Power High-Speed Short-Reach
      Alternative to TIA/EIA-485
    • Backplane or Cabled Multipoint Data and Clock Transmission
    • Cellular Base Stations
    • Central-Office Switches
    • Network Switches and Routers

(1) The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

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Description

The SN65MLVD201, 203, 206, and 207 are multipoint-low-voltage differential (M-LVDS) line drivers and receivers, which are optimized to operate at signaling rates up to 200 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30 , and incorporates controlled transition times to allow for stubs off of the backbone transmission line.

These devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a common-mode voltage range of –1 V to 3.4 V. The Type-1 receivers exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus, and other faults conditions. The devices are characterized for operation from –40°C to 85°C.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Multipoint-LVDS Line Driver and Receiver datasheet (Rev. C) Jan. 07, 2008
Application note How Far, How Fast Can You Operate MLVDS? Aug. 06, 2018
Application note Introduction to M-LVDS (TIA/EIA-899) (Rev. A) Jan. 03, 2013
User guide Multipoint-Low Voltage Differential Signaling (M-LVDS) EVM (Rev. B) Apr. 05, 2004
Application note M-LVDS Signaling Rate Versus Distance Apr. 09, 2003
Application note Interoperability of M-LVDS and BusLVDS Feb. 06, 2003
User guide 200 Mbps Multipoint-Low Voltage Differential Signaling (M-LVDS) EVM (Rev. A) Dec. 20, 2002
Application note Wired-Logic Signaling with M-LVDS Oct. 31, 2002
User guide Multipoint-Low Voltage Differential Signaling (M-LVDS) Evaluation Module Mar. 04, 2002
Application note TIA/EIA-485 and M-LVDS, Power and Speed Comparison Feb. 20, 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
149
EVALUATION BOARD Download
99
Description
This evaluation module is for the SN65MLVD203B and SN65MLVD204B, which are M-LVDS transceivers.
The SN65MLVD203B is a full-duplex transceiver, and the SN65MLVD204B is a half-duplex transceiver.
Features
  • Can combine MLVD20XBEVM boards to simulate multiple receiver nodes
  • Includes footprints for D package version of devices, so entire family of SN65MLVD20X transceivers can be evaluated
  • Flexible termination
  • This evaluation module has the complete circuit for the full-duplex and half-duplex M-LVDS (...)
EVALUATION BOARD Download
49
Description

The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (/RE). When /RE = low (...)

Features
  • Low-Voltage Differential 30Ω to 55Ω Line Data and Clock Receivers for Signaling Rates† up to Transmission via Backplanes and Cables 250 Mbps; Clock Frequencies up to 125 MHz
  • SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis
  • SN65MLVD3 Type-2 Receiver Provides 100 mV Offset (...)

Design tools & simulation

SIMULATION MODEL Download
SLLC117A.ZIP (16 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

CAD/CAE symbols

Package Pins Download
SOIC (D) 8 View options

Ordering & quality

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  • MSL rating/Peak reflow
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  • Qualification summary
  • Ongoing reliability monitoring

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