4-ch, 2-input, 4.75-V to 5.25-V bipolar NAND gates
Product details
Parameters
Package | Pins | Size
Features
- Package Options Include:
- Plastic Small-Outline (D, NS, PS)
- Shrink Small-Outline (DB)
- Ceramic Flat (W)
- Ceramic Chip Carriers (FK)
- Standard Plastic (N)
- Ceramic (J)
- Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package
- Inputs Are TTL Compliant; VIH = 2 V and
VIL = 0.8 V - Inputs Can Accept 3.3-V or 2.5-V Logic Inputs
- SN5400, SN54LS00, and SN54S00 are Characterized For Operation Over the Full Military Temperature Range of –55ºC to 125ºC
Description
The SNx4xx00 devices contain four independent,
2-input NAND gates. The devices perform the Boolean function Y = A .B or Y = A + B in positive logic.
Technical documentation
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View all 10 | Type | Title | Date | |
|---|---|---|---|
| * | Data sheet | SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates datasheet (Rev. D) | May 19, 2017 |
| Technical article | How to keep your motor running safely | Jun. 04, 2020 | |
| Selection guide | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Dec. 02, 2015 | |
| User guide | LOGIC Pocket Data Book (Rev. B) | Jan. 16, 2007 | |
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 | |
| More literature | Logic Cross-Reference (Rev. A) | Oct. 07, 2003 | |
| Application note | Designing With Logic (Rev. C) | Jun. 01, 1997 | |
| Application note | Input and Output Characteristics of Digital Integrated Circuits | Oct. 01, 1996 | |
| Application note | Live Insertion | Oct. 01, 1996 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
14-24-LOGIC-EVM
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Design tools & simulation
SDLM075.ZIP (7 KB) - PSpice Model
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 14 | View options |
| SOIC (D) | 14 | View options |
Ordering & quality
Information included:
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
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