SN7406

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6-ch, 4.75-V to 5.25-V bipolar inverters with open-collector outputs

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Product details

Parameters

Technology Family TTL VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Channels (#) 6 IOL (Max) (mA) 40 IOH (Max) (mA) 0 ICC (Max) (uA) 51000 Input type Bipolar Output type Open-Collector Features High speed (tpd 10-50ns) Rating Catalog open-in-new Find other Inverting buffer/driver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 open-in-new Find other Inverting buffer/driver

Features

  • Convert TTL Voltage Levels to MOS Levels
  • High Sink-Current Capability
  • Input Clamping Diodes Simplify System Design
  • Open-Collector Drivers for Indicator Lamps and Relays
  • Inputs Fully Compatible With Most TTL Circuits

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Description

These TTL hex inverter buffers/drivers feature high-voltage open-collector outputs for interfacing with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and also are characterized for use as inverter buffers for driving TTL inputs. The SN5406 and SN7406 have minimum breakdown voltages of 30 V. The SN5416 and SN7416 have minimum breakdown voltages of 15 V. The maximum sink current is 30 mA for the SN5406 and SN5416, and 40 mA for the SN7406 and SN7416.

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Technical documentation

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Type Title Date
* Datasheet Hex Inverter Buffers/Drivers With Open-Collector High-Voltage Outputs datasheet (Rev. A) Dec. 01, 2001
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SDLM071.ZIP (6 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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