Widebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes.
Data flow in each direction is controlled by output-enable (
and 
), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by
the clock-enable (
and 
) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high. When LEAB
is low, the A data is latched if CLKAB is held at a high or low logic
level. If LEAB is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB. Output enable is active low. When is low, the outputs are active.
When is high, the
outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses , LEBA, CLKBA, and .
To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
driver.
The SN54ABT16601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16601 is characterized for operation from -40°C to 85°C.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 8-Bit Universal Bus Transceivers With 3-State Outputs datasheet (Rev. C) | Jan 1, 1997 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SSOP (DL) | 56 | Ultra Librarian |
| TSSOP (DGG) | 56 | Ultra Librarian |
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.