SN74ABT16657

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16-Bit Transceivers With Parity Generators / Checkers And 3-State Outputs

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16-Bit Transceivers With Parity Generators / Checkers And 3-State Outputs

SN74ABT16657

ACTIVE

Product details

Parameters

Technology Family ABT IOL (Max) (mA) 64 IOH (Max) (mA) -32 Operating temperature range (C) -40 to 85 Rating Catalog open-in-new Find other General-purpose transceivers

Package | Pins | Size

SSOP (DL) 56 191 mm² 18.42 x 10.35 open-in-new Find other General-purpose transceivers

Features

  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

 

Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

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Description

The 'ABT16657 contain two noninverting octal transceiver sections with separate parity generator/checker circuits and control signals. For either section, the transmit/receive (1T/R\ or 2T/R\) input determines the direction of data flow. When 1T/R\ (or 2T/R\) is high, data flows from the 1A (or 2A) port to the 1B (or 2B) port (transmit mode); when 1T/R\ (or 2T/R\) is low, data flows from the 1B (or 2B) port to the 1A (or 2A) port (receive mode). When the output-enable (1 or 2) input is high, both the 1A (or 2A) and 1B (or 2B) ports are in the high-impedance state.

Odd or even parity is selected by a logic high or low level, respectively, on the 1ODD (or 2ODD) input. 1PARITY (or 2PARITY) carries the parity bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode.

In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or 2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD (or 2ODD) input. For example, if 1ODD is low (even parity selected) and there are five high bits on the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus bits plus parity bit) are high.

 

In the receive mode, after the 1B (or 2B) bus is polled to determine the number of high bits, the 1(or 2) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if 1ODD is high (odd parity selected), 1PARITY is high, and there are three high bits on the 1B bus, then 1 is low, indicating a parity error.

To ensure the high-impedance state during power up or power down, should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16657 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16657 is characterized for operation from -40°C to 85°C.

 

 

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Technical documentation

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Type Title Date
* Data sheet 16-Bit Transceivers w/ Parity Generators/Checkers & 3-State Outputs datasheet (Rev. B) Jan. 01, 1997
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) Jul. 26, 2021
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) Feb. 16, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
Selection guide Advanced Bus Interface Logic Selection Guide Jan. 09, 2001
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) Mar. 01, 1997
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) Dec. 01, 1996
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

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SSOP (DL) 56 View options

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