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Product details

Parameters

Technology Family ABT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Bits (#) 8 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 150 ICC @ nom voltage (Max) (mA) 38 Propagation delay (Max) (ns) 5.8 IOL (Max) (mA) 64 IOH (Max) (mA) -32 Operating temperature range (C) -40 to 85 open-in-new Find other JTAG boundary scan products

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 open-in-new Find other JTAG boundary scan products

Features

  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port
    and Boundary-Scan Architecture
  • Functionally Equivalent to 'F245 and 'ABT245 in the Normal-Function Mode
  • SCOPETM Instruction Set:
    • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
    • Parallel-Signature Analysis at Inputs With Masking Option
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Even-Parity Opcodes
  • Two Boundary-Scan Cells per I/O for Greater Flexibility
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline Packages (DW), Ceramic Chip Carriers(FK), and Standard Ceramic DIPs (JT)

    SCOPE and EPIC-IIB are trademarks of Texas Instruments Incorporated.


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Description

The 'ABT8245 scan test devices with octal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F245 and 'ABT245 octal bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable () inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. The output-enable () input can be used to disable the device so that the buses are effectively isolated.

 

In the test mode, the normal operation of the SCOPETM bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8245 is characterized for operation from -40°C to 85°C.

 

 

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Technical documentation

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No results found. Please clear your search and try again. View all 22
Type Title Date
* Datasheet Scan Test Devices With Octal Bus Transceivers datasheet (Rev. D) Dec. 01, 1996
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
User guides LASP Demo Board User's Guide Nov. 01, 2005
Application notes Programming CPLDs Via the 'LVT8986 LASP Nov. 01, 2005
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
Application notes Quad Flatpack No-Lead Logic Packages (Rev. D) Feb. 16, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) Mar. 01, 1997
Application notes Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SIMULATION MODELS Download
SCTM006.ZIP (2 KB) - BSDL Model

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options

Ordering & quality

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