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SN74AC11-EP

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Enhanced product 3-ch, 3-input, 2-V to 6-V AND gates

Data sheet
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Enhanced product 3-ch, 3-input, 2-V to 6-V AND gates

SN74AC11-EP

ACTIVE
Data sheet Order now

Product details

Parameters

Technology Family AC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Channels (#) 3 Inputs per channel 3 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 100 Rating HiRel Enhanced Product Operating temperature range (C) -40 to 85 open-in-new Find other AND gate

Package | Pins | Size

TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other AND gate

Features

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 6-V VCC Operation
  • Inputs Accept Voltages to 6 V
  • Max tpd of 7.5 ns at 5 V

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

 open-in-new Find other AND gate

Description

The SN74AC11 device contains three independent 3-input AND gates. This device performs the Boolean function Y = A • B • C or Y = (A\ + B\ + C\)\ in positive logic.

 open-in-new Find other AND gate
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 16
Type Title Date
* Datasheet SN74AC11-EP datasheet Jan. 06, 2004
* VID SN74AC11-EP VID V6204701 Jun. 21, 2016
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
More literature HiRel Unitrode Power Management Brochure Jul. 07, 2009
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
TSSOP (PW) 14 View options

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  • MSL rating/Peak reflow
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  • Qualification summary
  • Ongoing reliability monitoring

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