Product details

Technology Family AC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Number of channels (#) 6 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 20 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Rating Catalog
Technology Family AC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Number of channels (#) 6 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 20 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Rating Catalog
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • 2-V to 6-V VCC Operation
  • Inputs Accept Voltages to 6 V
  • Max tpd of 9.5 ns at 5 V

  • 2-V to 6-V VCC Operation
  • Inputs Accept Voltages to 6 V
  • Max tpd of 9.5 ns at 5 V

These Schmitt-trigger devices contain six independent inverters. They perform the Boolean function Y = A. Because of the Schmitt action, they have different input threshold levels for positive-going (VT+) and for negative-going (VT–) signals.

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean, jitter-free output signals. They also have a greater noise margin than conventional inverters.

These Schmitt-trigger devices contain six independent inverters. They perform the Boolean function Y = A. Because of the Schmitt action, they have different input threshold levels for positive-going (VT+) and for negative-going (VT–) signals.

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean, jitter-free output signals. They also have a greater noise margin than conventional inverters.

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Technical documentation

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Type Title Date
* Data sheet SN54AC14, SN74AC14 datasheet (Rev. G) 05 Aug 2008
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Understanding Schmitt Triggers 21 Sep 2011
More literature HiRel Unitrode Power Management Brochure 07 Jul 2009
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, P, N, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
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Limit: 5
Simulation model

SN74AC14 Behavioral SPICE Model

SCAM136.ZIP (7 KB) - PSpice Model
Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options

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