SN74AC240-Q1

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Automotive Catalog Octal Buffers/Drivers With 3-State Outputs

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Automotive Catalog Octal Buffers/Drivers With 3-State Outputs

SN74AC240-Q1

ACTIVE

Product details

Parameters

Technology Family AC VCC (Min) (V) 2 VCC (Max) (V) 6 Channels (#) 8 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 40 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Data rate (Mbps) 200 Rating Automotive open-in-new Find other Inverting buffer/driver

Package | Pins | Size

TSSOP (PW) 20 42 mm² 6.5 x 6.4 open-in-new Find other Inverting buffer/driver

Features

  • Qualified for Automotive Applications
  • 2-V to 6-V VCC Operation
  • Inputs Accept Voltages to 6 V
  • Max tpd of 6.5 ns at 5 V

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Description

This octal buffer and line driver is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74AC240 device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Octal Buffer/Driver With 3-State Outputs datasheet (Rev. A) Jan. 22, 2008
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
More literature Automotive Logic Devices Brochure Aug. 27, 2014
More literature HiRel Unitrode Power Management Brochure Jul. 07, 2009
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCAM135.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 20 View options

Ordering & quality

Support & training

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