The ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements.
The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction.
The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.
|Part number||Order||Bits (#)||High input voltage (Min) (Vih)||High input voltage (Max) (Vih)||Output voltage (Min) (V)||Output voltage (Max) (V)||IOH (Max) (mA)||IOL (Max) (mA)||Features||Package Group||Rating|
Partial power down (Ioff)
SOIC | 20
SO | 20
SSOP | 20
TSSOP | 20