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SN74AHC00-EP

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Enhanced product 4-ch, 2-input, 2-V to 5.5-V NAND gates

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Enhanced product 4-ch, 2-input, 2-V to 5.5-V NAND gates

SN74AHC00-EP

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Data sheet Order now

Product details

Parameters

Technology Family AHC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 50 IOH (Max) (mA) -50 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 110 Rating HiRel Enhanced Product Operating temperature range (C) -55 to 125 open-in-new Find other NAND gate

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other NAND gate

Features

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification Qualification Pedigree
  • EPIC™ (Enhanced-Performance Implanted CMOS) Process

EPIC is a trademark of Texas Instruments.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life.

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Description

The SN74AHC00 performs the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Quadruple 2-Input Positive-NAND Gate datasheet Jul. 23, 2002
* Radiation & reliability report SN74AHC00MDREP Reliability Report Aug. 09, 2016
* VID SN74AHC00-EP VID V6203604 Jun. 21, 2016
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) Dec. 02, 2002
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guide AHC/AHCT Designer's Guide February 2000 (Rev. D) Feb. 24, 2000
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) Apr. 01, 1998
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) Apr. 01, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

CAD/CAE symbols

Package Pins Download
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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