SN74AHC126 Quadruple Bus Buffer Gates With 3-State Outputs | TI.com

SN74AHC126
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Quadruple Bus Buffer Gates With 3-State Outputs

Quadruple Bus Buffer Gates With 3-State Outputs - SN74AHC126
Datasheet
 

Description

The ’AHC126 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

Features

  • Operating Range 2-V to 5.5-V VCC
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Package Group
SN74AHC126 Order now AHC     2     5.5     4     8     -8     40     Standard CMOS     3-State     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs    
220     Catalog     PDIP | 14
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14
TVSOP | 14    
SN54AHC126 Samples not available AHC     2     5.5     4     8     -8     40     Standard CMOS     3-State     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs    
220     Military     CFP | 14
LCCC | 20