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Product details

Parameters

Technology Family AHC VCC (Min) (V) 2 VCC (Max) (V) 5.5 Channels (#) 6 IOL (Max) (mA) 8 IOH (Max) (mA) -8 ICC (Max) (uA) 20 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Unbuffered Data rate (Mbps) 140 Rating Catalog open-in-new Find other Inverting buffer/driver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Inverting buffer/driver

Features

  • Operating Range 2-V to 5.5-V VCC
  • Unbuffered Outputs
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Description

The ’AHCU04 devices contain six independent inverters. These devices perform the Boolean function Y = A\. Internal circuitry consists of single-stage inverters that can be used in analog applications such as crystal oscillators.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN54AHCU04, SN74AHCU04 datasheet (Rev. K) Jul. 09, 2003
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) Dec. 02, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guides AHC/AHCT Designer's Guide February 2000 (Rev. D) Feb. 24, 2000
Application notes Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) Apr. 01, 1998
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) Apr. 01, 1998
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARDS Download
document-generic User guide
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

Design tools & simulation

SIMULATION MODELS Download
SCLJ014.ZIP (120 KB) - HSpice Model
SIMULATION MODELS Download
SCLM066A.ZIP (25 KB) - IBIS Model
SIMULATION MODELS Download
SCLM236.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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