SN74ALS20A

ACTIVE

Dual 4-Input Positive-NAND Gates

Top

Product details

Parameters

Technology Family ALS VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 2 Inputs per channel 4 IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 Input type Bipolar Output type Push-Pull Features High Speed (tpd 10-50ns) Data rate (Max) (Mbps) 75 Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other NAND gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 open-in-new Find other NAND gate

Features

  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

open-in-new Find other NAND gate

Description

These devices contain two independent 4-input positive-NAND gates. They perform the Boolean functionsor \ in positive logic.

The SN54ALS20A and SN54AS20 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS20A and SN74AS20 are characterized for operation from 0°C to 70°C.

 

 

open-in-new Find other NAND gate
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 13
Type Title Date
* Datasheet Dual 4-Input Positive-NAND Gates datasheet (Rev. B) Dec. 01, 1994
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos