SN74ALS35A

ACTIVE

Hex Noninverters with Open-Collector Outputs

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Product details

Parameters

Technology Family ALS VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 6 IOL (Max) (mA) 8 ICC (Max) (uA) 6300 IOH (Max) (mA) 0 Input type Bipolar Output type Open-Collector Features Very high speed (tpd 5-10ns) Data rate (Mbps) 150 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other Non-Inverting buffer/driver

Features

  • Noninverter With Open-Collector Outputs
  • Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic (N) 300-mil DIPs

 

open-in-new Find other Non-Inverting buffer/driver

Description

The SN74ALS35A contains six independent noninverters with open-collector outputs. They perform the Boolean function Y = A. The open-collector outputs require pullup resistors to perform correctly. These outputs may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOH levels.

The SN74ALS35A is characterized for operation from 0°C to 70°C.

 

 

open-in-new Find other Non-Inverting buffer/driver
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Hex Noninverter With Open-Collector Outputs datasheet (Rev. C) Dec. 01, 1994
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SDAM062.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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