SN74AS645

ACTIVE

Octal Bus Transceivers With 3-State Outputs

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Product details

Parameters

Technology Family AS VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Bits (#) 8 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 125 ICC @ nom voltage (Max) (mA) 0.055 tpd @ nom Voltage (Max) (ns) 10 IOL (Max) (mA) 64 IOH (Max) (mA) -15 Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other Standard transceiver

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 open-in-new Find other Standard transceiver

Features

  • Bidirectional Bus Transceivers in High-Density 20-Pin Packages
  • True Logic
  • 3-State Outputs
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

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Description

These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the level at the direction-control (DIR) input. The output-enable input can be used to disable the device so that the buses are effectively isolated.

The -1 version of the SN74ALS645A is identical to the standard version, except that the recommended maximum IOL is increased to 48 mA. There is no -1 version of the SN54ALS645A.

The SN54ALS645A and SN54AS645 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS645A and SN74AS645 are characterized for operation from 0°C to 70°C.

 

 

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Technical documentation

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Type Title Date
* Datasheet Octal Bus Transceivers With 3-State Outputs datasheet Jan. 01, 1995
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Solution guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Advanced Schottky Load Management Feb. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options

Ordering & quality

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Videos

Anatomy of a logic part number

Logic part numbers use a formulaic naming system to denote the device's functionality and features. This video reviews the components to a logic part's name.

Posted: 22-Jan-2018
Duration: 01:26

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