SN74AUC17

ACTIVE

Hex Schmitt-Trigger Buffer

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Product details

Parameters

Technology Family AUC VCC (Min) (V) 0.8 VCC (Max) (V) 2.7 Channels (#) 6 IOL (Max) (mA) 9 IOH (Max) (mA) -9 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Ultra high speed (tpd <5ns), Partial power down (Ioff), Over-voltage tolerant inputs Data rate (Mbps) 500 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other Non-Inverting buffer/driver

Features

  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 1.8 ns at 1.8 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Description

This hex Schmitt-trigger buffer is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC17 contains six independent buffers and performs the Boolean function Y = A. The device functions as six independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Datasheet SN74AUC17 datasheet (Rev. A) Mar. 28, 2005
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Understanding Schmitt Triggers Sep. 21, 2011
Solution guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices Mar. 21, 2003
User guides AUC Data Book, January 2003 (Rev. A) Jan. 01, 2003
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature AUC Product Brochure (Rev. A) Mar. 18, 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODELS Download
SCEM372.ZIP (54 KB) - IBIS Model
SIMULATION MODELS Download
SCEM732.ZIP (7 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
16-Bit 1-MSPS Data Acquisition Reference Design, Isolated for High-Voltage Common-Mode Rejection
TIDA-00106 — The circuit represents a high-performance data acquisition (DAQ) solution suitable for processing input signals (up to ±12 V) superimposed on large common-mode offsets (tested up to 155 Vp-p from dc to approximately 15 kHz) relative to the ground potential of the system's main power supply (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Power Solution for Terasic DE0-Nano (Cyclone IV) - Reference Design
PMP10580 The PMP10580 reference design provides all the power supply rails necessary to power Altera’s Cyclone® IV FPGA.  DE0-Nano was developed by Terasic and this board is available for purchase through Terasic’s website.
document-generic Schematic document-generic User guide
Design files

CAD/CAE symbols

Package Pins Download
VQFN (RGY) 14 View options

Ordering & quality

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