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IEEE Std 1149.1 (JTAG) Boundary-Scan Test Device With Octal D-Type Latches

SN74BCT8373A

ACTIVE

Product details

Parameters

Technology Family BCT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State IOL (Max) (mA) 64 IOH (Max) (mA) -15 open-in-new Find other JTAG boundary scan products

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 open-in-new Find other JTAG boundary scan products

Features

  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Octal Test-Integrated Circuits
  • Functionally Equivalent to 'F373 and 'BCT373 in the Normal-Function Mode
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • Test Operation Synchronous to Test Access Port (TAP)
  • Implement Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V) on TMS Pin
  • SCOPETM Instruction Set
    • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
    • Parallel Signature Analysis at Inputs
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic and Ceramic 300-mil DIPs (JT, NT)

    SCOPE is a trademark of Texas Instruments Incorporated.

     

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Description

The 'BCT8373A scan test devices with octal D-type latches are members of the Texas Instruments SCOPETM testability integrated-
circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F373 and 'BCT373 octal D-type latches. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal latches.

In the test mode, the normal operation of the SCOPETM octal latches is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations, as described in IEEE Standard 1149.1-1990.

 

Four dedicated test terminals are used to control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54BCT8373A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT8373A is characterized for operation from 0°C to 70°C.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 14
Type Title Date
* Datasheet Scan Test Devices With Octal D-Type Latches datasheet (Rev. F) Jul. 01, 1996
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
User guide LASP Demo Board User's Guide Nov. 01, 2005
Application note Programming CPLDs Via the 'LVT8986 LASP Nov. 01, 2005
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996

Design & development

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Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCTM004.ZIP (2 KB) - BSDL Model
SIMULATION TOOL Download

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options

Ordering & quality

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