SN74CBT6800A

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Product details

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SOIC (DW) 24 160 mm² 15.5 x 10.3 TSSOP (PW) 24 34 mm² 4.4 x 7.8
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Outputs Are Precharged by Bias Voltage to Minimize Signal Distortion During Live Insertion
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Outputs Are Precharged by Bias Voltage to Minimize Signal Distortion During Live Insertion

The SN74CBT6800A provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows bidirectional connections to be made while adding near-zero propagation delay. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise.

The SN74CBT6800A is organized as one 10-bit switch with a single enable (ON\) input. When ON\ is low, the switch is on, and port A is connected to port B. When ON\ is high, the switch between port A and port B is open. When ON\ is high or VCC is 0 V, B port is precharged to BIASV through the equivalent of a 10-k resistor.

The SN74CBT6800A provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows bidirectional connections to be made while adding near-zero propagation delay. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise.

The SN74CBT6800A is organized as one 10-bit switch with a single enable (ON\) input. When ON\ is low, the switch is on, and port A is connected to port B. When ON\ is high, the switch between port A and port B is open. When ON\ is high or VCC is 0 V, B port is precharged to BIASV through the equivalent of a 10-k resistor.

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Technical documentation

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Type Title Date
* Data sheet 10-Bit FET Bus Switch With Precharged Outputs datasheet (Rev. N) 15 Mar 2001
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. D) 09 Dec 2021
Application note Multiplexers and Signal Switches Glossary (Rev. B) 01 Dec 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Digital Bus Switch Selection Guide (Rev. A) 10 Nov 2004
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
More literature CBT RAID Application Clip 12 Jun 2003
Application note Bus FET Switch Solutions for Live Insertion Applications 07 Feb 2003
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Flexible Voltage-Level Translation With CBT Family Devices 20 Jul 1999
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 01 Dec 1998
Application note 3.3-V to 2.5-V Translation with Texas Instruments Crossbar Technology (Rev. A) 03 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note 5-V To 3.3-V Translation With the SN74CBTD3384 (Rev. B) 01 Mar 1997
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

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Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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TSSOP (PW) 24 View options

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