SN74CBTS6800

ACTIVE

5-V, 1:1 (SPST), 10-channel general-purpose FET bus switch with pre-charged outputs

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5-V, 1:1 (SPST), 10-channel general-purpose FET bus switch with pre-charged outputs

SN74CBTS6800

ACTIVE

Product details

Parameters

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Package | Pins | Size

TSSOP (PW) 24 34 mm² 4.4 x 7.8 TVSOP (DGV) 24 32 mm² 5 x 6.4 open-in-new Find other Analog switches & muxes

Features

  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Outputs Are Precharged by Bias Voltage to Minimize Signal Distortion During Live Insertion
  • Schottky Diodes on the I/Os to Clamp Undershoots up to -2 V
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Description

The SN74CBTS6800 provides ten bits of high-speed TTL-compatible bus switching with Schottky diodes on the I/Os to clamp undershoots.

The low on-state resistance of the switch allows bidirectional connections to be made, while adding near-zero propagation delay. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise.

The SN74CBTS6800 is organized as one 10-bit switch with a single enable (ON\) input. When ON\ is low, the switch is on, and port A is connected to port B. When ON\ is high, the switch between port A and port B is open. When ON\ is high or VCC is 0 V, B port is precharged to BIASV through the equivalent of a 10-k resistor.

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Technical documentation

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Type Title Date
* Datasheet 10-Bit FET Bus Switch With Precharged Outputs And Schottky Diode Clamping datasheet (Rev. C) Oct. 20, 2000
Application note Selecting the Right Texas Instruments Signal Switch (Rev. B) Apr. 02, 2020
Application note Multiplexers and Signal Switches Glossary Mar. 06, 2020
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Digital Bus Switch Selection Guide (Rev. A) Nov. 10, 2004
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
More literature CBT RAID Application Clip Jun. 12, 2003
Application note Bus FET Switch Solutions for Live Insertion Applications Feb. 07, 2003
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application note Flexible Voltage-Level Translation With CBT Family Devices Jul. 20, 1999
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) Dec. 01, 1998
Application note 3.3-V to 2.5-V Translation with Texas Instruments Crossbar Technology (Rev. A) Apr. 03, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note 5-V To 3.3-V Translation With the SN74CBTD3384 (Rev. B) Mar. 01, 1997
Application note Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

INTERFACE ADAPTER Download
10
Description

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Features
  • Quick testing of TI's leaded surface mount packages 
  • Allows leaded suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 8 most popular leaded packages with a single panel


Design tools & simulation

SIMULATION MODEL Download
SCDJ037.ZIP (118 KB) - HSpice Model

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 24 View options
TVSOP (DGV) 24 View options

Ordering & quality

Information included:
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  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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