SN74F125

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4-ch, 4.5-V to 5.5-V bipolar buffers with 3-state outputs

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Product details

Parameters

Technology Family F Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 4 IOL (Max) (mA) 64 ICC (Max) (uA) 40000 IOH (Max) (mA) -15 Input type Bipolar Output type 3-State Features Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 open-in-new Find other Non-Inverting buffer/driver

Features

  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

open-in-new Find other Non-Inverting buffer/driver

Description

The SN74F125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.

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Technical documentation

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Type Title Date
* Data sheet Quadruple Bus Buffer Gate With 3-State Outputs datasheet (Rev. B) Jul. 03, 2002
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SDFM006A.ZIP (6 KB) - IBIS Model
SIMULATION MODEL Download
SDFM020.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options

Ordering & quality

Information included:
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  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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