Octal Transceiver With Parity Generator/Checker and 3-State Outputs


Product details


Technology Family F VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Bits (#) 8 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 70 ICC @ nom voltage (Max) (mA) 0.15 Propagation delay (Max) (ns) 8 IOL (Max) (mA) 64 IOH (Max) (mA) -15 Operating temperature range (C) 0 to 70 open-in-new Find other Parity transceiver

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 open-in-new Find other Parity transceiver


  • Combines ´F245 and ´F280B Functions in One Package
  • High-Impedance N-P-N Inputs for Reduced Loading (70 uA in Low and High States)
  • High Output Drive and Light Bus Loading
  • 3-State B Outputs Sink 64 mA and Source 15 mA
  • Input Diodes for Termination Effects
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs


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The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port.

The transmit/receive (T/R\) input determines the direction of the data flow through the bidirectional transceivers. When T/R\ is high, data is transmitted from the A port to the B port. When T/R\ is low, data is received at the A port from the B port.

When the output enable () input is high, both the A and B ports are placed in a high-impedance state (disabled). The ODD/EVEN\ input allows the user to select between odd or even parity systems. When transmitting from A port to B port (T/R\ high), PARITY is an output from the generator/checker. When receiving from B port to A port (T/R\ low), PARITY is an input.

When transmitting (T/R\ high), the parity select (ODD/EVEN\) input is made high or low as appropriate. The A port is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by ODD/EVEN\ and the number of high bits on A port. When ODD/EVEN\ is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity.

When in the receive mode (T/R\ low), the B port is polled to determine the number of high bits. If ODD/EVEN\ is low (for even parity) and the number of highs on B port is:

  1. 1. Odd and the PARITY input is high, then ERR\ will be high signifying no error.
  2. 2. Even and the PARITY input is high, then ERR\ will be low indicating an error.

The SN74F657 is characterized for operation from 0°C to 70°C.



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Technical documentation

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Type Title Date
* Datasheet Octal Transceiver With Parity Generator/Checker And 3-State Outputs datasheet (Rev. A) Oct. 01, 1993
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996

Design & development

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Hardware development

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

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SOIC (DW) 24 View options

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