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Product details

Parameters

Technology Family GTL Applications SDIO, MDIO, SMBus, PMBus Bits (#) 10 IOH (Max) (mA) 64 IOL (Max) (mA) 64 open-in-new Find other GTL, TTL, BTL & ECL transceivers & translators

Package | Pins | Size

TSSOP (PW) 24 34 mm² 4.4 x 7.8 open-in-new Find other GTL, TTL, BTL & ECL transceivers & translators

Features

  • Provides Bidirectional Voltage Translation With No Direction Control Required
  • Allows Voltage Level Translation From 1 V up to 5 V
  • Provides Direct Interface With GTL, GTL+, LVTTL/TTL, and 5-V CMOS Levels
  • Low On-State Resistance Between Input and Output Pins (Sn/Dn)
  • Supports Hot Insertion
  • No Power Supply Required — Will Not Latch Up
  • 5-V-Tolerant Inputs
  • Low Standby Current
  • Flow-Through Pinout for Ease of Printed Circuit Board Trace Routing
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-4)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Bidirectional or Unidirectional Applications Requiring Voltage-Level Translation From Any Voltage (1 V to 5 V) to Any Voltage (1 V to 5 V)
    • Low Voltage Processor I2C Port Translation to 3.3-V and/or 5-V I2C Bus Signal Levels
    • GTL/GTL+ Translation to LVTTL/TTL Signal Levels

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Description

The GTL2010 provides ten NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).

When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pullup resistors.

All transistors in the GTL2010 have the same electrical characteristics, and there is minimal deviation from one output to another in voltage or propagation delay. This offers superior matching over discrete transistor voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being identical, the reference transistor (SREF/DREF) can be located on any of the other ten matched Sn/Dn transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides excellent ESD protection.

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Technical documentation

= Featured
No results found. Please clear your search and try again. View all 14
Type Title Date
* Datasheet GTL2010 datasheet Feb. 16, 2006
Selection guides Voltage translation buying guide Jun. 13, 2019
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
User guides GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) Sep. 15, 2001
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001
Application notes GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A) Mar. 01, 1997
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 24 View options

Ordering & quality

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