12-Bit GTL-/GTL/GTL+ To LVTTL Translator


Product details


Technology Family GTL VCC (Min) (V) 3 VCC (Max) (V) 3.6 Channels (#) 12 IOL (Max) (mA) 16 IOH (Max) (mA) -16 ICC (uA) 12000 Input type GTL/GTL-/GTL+/LVTTL Output type GTL/GTL-/GTL+/LVTTL Features Balanced Outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Damping resistors Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Universal bus transceiver (UBT)

Package | Pins | Size

TSSOP (PW) 28 62 mm² 9.7 x 6.4 open-in-new Find other Universal bus transceiver (UBT)


  • Operates as a GTL-/GTL/GTL+ to LVTTL or LVTTL to GTL-/GTL/GTL+ Translator
  • Series Termination on TTL Output of 30
  • Latch-Up Testing Done to JEDEC Standard JESD 78
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Xeon is a trademark of Intel Corporation.

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The SN74GTL2107 is a 12-bit translator that interfaces between the 3.3-V LVTTL chip set I/O and the Xeon™ processor GTL-/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications.

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Technical documentation

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Type Title Date
* Datasheet SN74GTL2107 datasheet Jul. 01, 2006
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
User guides GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) Sep. 15, 2001
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001
Application notes GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A) Mar. 01, 1997
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

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Design tools & simulation

SCLM102.ZIP (109 KB) - HSpice Model
SLLM075.ZIP (32 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 28 View options

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