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8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver with Split LVTTL Port and Feedback Path

SN74GTLP22033

ACTIVE

Product details

Parameters

Technology Family GTLP Applications GTL Bits (#) 8 IOH (Max) (mA) -24 IOL (Max) (mA) 24 open-in-new Find other GTL, TTL, BTL & ECL transceivers & translators

Package | Pins | Size

TSSOP (DGG) 48 101 mm² 12.5 x 8.1 open-in-new Find other GTL, TTL, BTL & ECL transceivers & translators

Features

  • Member of the Texas Instruments Widebus™ Family
  • TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
  • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
  • Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
  • Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring
  • AO Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • LVTTL Interfaces Are 5-V Tolerant
  • High-Drive GTLP Open-Drain Outputs (100 mA)
  • Reduced LVTTL Outputs (-12 mA/12 mA)
  • Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
  • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.

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Description

The SN74GTLP22033 is a high-drive, 8-bit, three-wire registered transceiver that provides inverted LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and diagnostics monitoring, the same functionality as the SN74FB2033. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 .

The AO outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP22033 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL Applications, literature number SCEA017.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and can be directly driven by TTL or 5-V CMOS devices. VREF is the B-port differential input reference voltage.

This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between low and high adjusts the B-port output rise and fall times.This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OEAB\ should be tied to VCC through a pullup resistor and OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet 8-Bit LVTTL-to-GTLP Adj.-Edge-Rate Regstd.Xcvr W/ Split LVTTL Port&Feedbk Path datasheet (Rev. C) Sep. 04, 2001
Selection guide Voltage translation buying guide Jun. 13, 2019
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
Application note Logic in Live-Insertion Applications With a Focus on GTLP Jan. 14, 2002
User guide GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) Sep. 15, 2001
Application note Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP) Apr. 05, 2001
Selection guide Advanced Bus Interface Logic Selection Guide Jan. 09, 2001
Application note Texas Instruments GTLP Frequently Asked Questions Jan. 01, 2001
Application note Fast GTLP Backplanes With the GTLPH1655 (Rev. A) Sep. 19, 2000
More literature High Level Brochure of Gunning Transceiver Logic Plus Jan. 14, 2000

Design & development

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