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8-Bit LVTTL-to-GTLP Bus Transceiver

SN74GTLPH306

ACTIVE

Product details

Parameters

Technology Family GTLP Applications GTL Bits (#) 8 IOH (Max) (mA) -24 IOL (Max) (mA) 24 open-in-new Find other GTL, TTL, BTL & ECL transceivers & translators

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 TSSOP (PW) 24 34 mm² 4.4 x 7.8 TVSOP (DGV) 24 32 mm² 5 x 6.4 open-in-new Find other GTL, TTL, BTL & ECL transceivers & translators

Features

  • TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
  • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
  • Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
  • LVTTL Interfaces Are 5-V Tolerant
  • Medium-Drive GTLP Outputs (50 mA)
  • LVTTL Outputs (\x9624 mA/24 mA)
  • GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on A-Port Data Inputs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

OEC, TI, and TI-OPC are trademarks of Texas Instruments.

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Description

The SN74GTLPH306 is a medium-drive, 8-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 .

GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH306 is given only at the preferred higher-noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE\) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 16
Type Title Date
* Datasheet 8-Bit LVTTL-to-GTL+ Bus Transceiver datasheet (Rev. E) Aug. 14, 2001
Selection guides Voltage translation buying guide Jun. 13, 2019
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
Application notes Logic in Live-Insertion Applications With a Focus on GTLP Jan. 14, 2002
User guides GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) Sep. 15, 2001
Application notes Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP) Apr. 05, 2001
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001
Application notes Texas Instruments GTLP Frequently Asked Questions Jan. 01, 2001
Application notes Fast GTLP Backplanes With the GTLPH1655 (Rev. A) Sep. 19, 2000
More literature High Level Brochure of Gunning Transceiver Logic Plus Jan. 14, 2000

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCEM202.ZIP (24 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options
TSSOP (PW) 24 View options
TVSOP (DGV) 24 View options

Ordering & quality

Support & training

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