SN74HC10-EP

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Enhanced Product Triple 3-Input Positive-Nand Gates

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Product details

Parameters

Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Channels (#) 3 Inputs per channel 3 IOL (Max) (mA) 5.2 IOH (Max) (mA) -5.2 Input type Standard CMOS Output type Push-Pull Features High Speed (tpd 10-50ns) Data rate (Max) (Mbps) 28 Rating HiRel Enhanced Product Operating temperature range (C) -40 to 125 open-in-new Find other NAND gate

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other NAND gate

Features

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 20-µA Max ICC
  • Typical tpd = 9 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

open-in-new Find other NAND gate

Description

The SN74HC10 device contains three independent 3-input NAND gates. It performs the Boolean function Y = (A • B • C)\ or Y = A\ + B\ + C\ in positive logic.

open-in-new Find other NAND gate
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN74HC10-EP datasheet Jan. 06, 2004
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
VID SN74HC10-EP VID V6204688 Jun. 21, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
SOIC (D) 14 View options
TSSOP (PW) 14 View options

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