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Noninverting buffers & drivers

SN74HC125

ACTIVE

4-ch, 2-V to 6-V buffers with 3-state outputs

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Data sheet

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SN74HCS125 ACTIVE Schmitt-trigger inputs quadruple bus buffer gates with 3-state outputs Pin-to-pin upgrade with Schmitt-triggers and improved performance

SN74HC125

ACTIVE
Data sheet Order now

Product details

Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 4 IOL (max) (mA) 6 Supply current (max) (µA) 80 IOH (max) (mA) -6 Input type Standard CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 4 IOL (max) (mA) 6 Supply current (max) (µA) 80 IOH (max) (mA) -6 Input type Standard CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Buffered inputs
  • Wide operating voltage range: 2 V to 6 V
  • Wide operating temperature range: –40°C to +85°C
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs
  • Buffered inputs
  • Wide operating voltage range: 2 V to 6 V
  • Wide operating temperature range: –40°C to +85°C
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs

This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic.

This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic.
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Technical documentation

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Type Title Date
* Data sheet SNx4HC125 Quadruple Buffers with 3-State Outputs datasheet (Rev. F) 30 Apr 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74HC125 Behavioral SPICE Model

SCLM225.ZIP (7 KB) - PSpice Model
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Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options
SOP (NS) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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