SN74HC125

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Quadruple Bus Buffer Gates With 3-State Outputs

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Product details

Parameters

Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Channels (#) 4 IOL (Max) (mA) 6 ICC (Max) (uA) 80 IOH (Max) (mA) -6 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Data rate (Mbps) 56 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Non-Inverting buffer/driver

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • High-Current 3-State Outputs Interface Directly
    With System Bus or Can Drive Up to 15 LSTTL
    Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 11 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Maximum
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Description

The SNx4HC125 device is a quadruple set of bus buffer gates and features independent line drivers with 3-state outputs. The SNx4HC125 is designed for 2-V to 6-V VCC operation. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SNx4HC125 Quadruple Bus Buffer Gates With 3-State Outputs datasheet (Rev. E) Dec. 23, 2015
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCLM225.ZIP (7 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
RGB-LED driver with microcontroller-based color mixing
PMP7247 — This design contains three TPS92551 LED-driver modules (buck topology) which can be independently PWM-modulated by a microcontroller for color mixing or dimming. The maximum input voltage is 50V and the circuit offers the possibility, to use several driver boards in master-slave configuration.

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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