SN74HC132

ACTIVE

Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs

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Product details

Parameters

Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Channels (#) 4 Inputs per channel 4 IOL (Max) (mA) 5.2 IOH (Max) (mA) -5.2 Input type Schmitt-Trigger Output type Push-Pull Features High Speed (tpd 10-50ns) Data rate (Max) (Mbps) 28 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other NAND gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other NAND gate

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive up to 10 LSTTL Loads
  • Low Power Consumption, 20-µA Maximum ICC
  • Typical tpd = 14 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Maximum
  • Operation from Very Slow Input Transitions
  • Temperature-Compensated Threshold Levels
  • High Noise Immunity
  • Same Pinouts as SN74HC00
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Description

The SNx4HC132 device functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive and negative going signals. The SNx4HC132 devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

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Technical documentation

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Type Title Date
* Datasheet SNx4HC132 Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs datasheet (Rev. G) Jun. 30, 2016
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCLM223.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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