Product details

Technology Family HC IOL (Max) (mA) 6 IOH (Max) (mA) -6 Operating temperature range (C) -40 to 85 Rating Catalog
Technology Family HC IOL (Max) (mA) 6 IOH (Max) (mA) -6 Operating temperature range (C) -40 to 85 Rating Catalog
PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2 TSSOP (PW) 20 29 mm² 6.5 x 4.4 TSSOP (PW) 20 29 mm² 4.4 x 6.5
  • Wide Operating Voltage Range of 2 V to 6 V
  • High-Current 3-State Outputs Drive Bus Lines Directly or Up to 15 LSTTL Loads
  • Low Power Consumption, 80-μA Max ICC
  • Typical tpd = 12 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 μA Max
  • On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

All trademarks are the property of their respective owners.

  • Wide Operating Voltage Range of 2 V to 6 V
  • High-Current 3-State Outputs Drive Bus Lines Directly or Up to 15 LSTTL Loads
  • Low Power Consumption, 80-μA Max ICC
  • Typical tpd = 12 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 μA Max
  • On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

All trademarks are the property of their respective owners.

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

 

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

 

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Technical documentation

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Type Title Date
* Data sheet SNx4HC245 Octal Bus Transceivers With 3-State Outputs datasheet (Rev. E) 30 Sep 2015
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application note Optimizing AC Drive Control Panel Systems With Logic and Translation Use Cases 20 Jan 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

In stock
Limit: 5
Reference designs

PMP10581 — Power Solution for Terasic DE2-115 (Cyclone IV)

The PMP10581 reference design provides all the power supply rails necessary to power Altera’s Cyclone® IV E FPGA. DE2-115 was developed by Terasic and this board is available for purchase through Terasic’s website.
Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options
TSSOP (PW) 20 View options

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