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SN74HC4066

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5-V, 2:1 (SPDT), 4-channel analog switch

Data sheet
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5-V, 2:1 (SPDT), 4-channel analog switch

SN74HC4066

ACTIVE
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Product details

Parameters

Configuration 1:1 SPST Number of channels (#) 4 Power supply voltage - single (V) 2.5, 3.3, 5 Ron (Typ) (Ohms) 30 ON-state leakage current (Max) (µA) 5 Bandwidth (MHz) 30 Operating temperature range (C) -40 to 85 Input/output continuous current (Max) (mA) 25 Rating Catalog CON (Typ) (pF) 3 Supply current (Typ) (uA) 2 open-in-new Find other Analog switches & muxes

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Analog switches & muxes

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Typical Switch Enable Time of 18 ns
  • Low Power Consumption, 20-µA Maximum ICC
  • Low Input Current of 1 µA Maximum
  • High Degree of Linearity
  • High On-Off Output-Voltage Ratio
  • Low Crosstalk Between Switches
  • Low On-State Impedance: 50-Ω Typical at
    VCC = 6 V
  • Individual Switch Controls

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Description

The SN74HC4066 device is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital signals. Each switch permits signals with amplitudes of up to 6 V (peak) to be transmitted in either direction.

Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the associated switch section.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 17
Type Title Date
* Datasheet SN74HC4066 quadruple bilateral analog switch datasheet (Rev. J) Mar. 14, 2019
Application note Selecting the Right Texas Instruments Signal Switch (Rev. B) Apr. 02, 2020
Application note Multiplexers and Signal Switches Glossary Mar. 06, 2020
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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Hardware development

INTERFACE ADAPTER Download
document-generic User guide
10
Description

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Features
  • Quick testing of TI's leaded surface mount packages 
  • Allows leaded suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 8 most popular leaded packages with a single panel


View details

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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