Product details

Technology Family HCS Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Number of channels (#) 4 IOL (Max) (mA) 7.8 ICC (Max) (uA) 2 IOH (Max) (mA) -7.8 Input type Schmitt-Trigger Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Rating Catalog
Technology Family HCS Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Number of channels (#) 4 IOL (Max) (mA) 7.8 ICC (Max) (uA) 2 IOH (Max) (mA) -7.8 Input type Schmitt-Trigger Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Rating Catalog
SOIC (D) 14 52 mm² 8.65 x 6 SOT-23-THN (DYY) 14 8 mm² 4.2 x 2 TSSOP (PW) 14 32 mm² 5 x 6.4 WQFN (BQA) 14 8 mm² 3 x 2.5
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • Extended ambient temperature range: –40°C to +125°C, TA
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • Extended ambient temperature range: –40°C to +125°C, TA

The SN74HCS125 contains four independent buffers with 3-state outputs and Schmitt-trigger inputs. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a Hi-Z state by applying a High on the OE pin.

The SN74HCS125 contains four independent buffers with 3-state outputs and Schmitt-trigger inputs. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a Hi-Z state by applying a High on the OE pin.

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Technical documentation

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* Data sheet SN74HCS125 Quadruple Buffer with 3-State Outputs and Schmitt-Trigger Inputs datasheet (Rev. C) PDF | HTML 11 May 2022
Application note Optimizing Board Space for Discrete LOGIC Designs Using Smallest Package Solutio (Rev. A) PDF | HTML 29 Sep 2022
Application note Enabling Optimal Solar Inverter Power Stage Designs with Logic PDF | HTML 17 Aug 2021

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74HCS125 Behavioral SPICE Model

SCLM311.ZIP (10 KB) - PSpice Model
Simulation model

SN74HCS125 IBIS Model (Rev. B)

SCLM174B.ZIP (51 KB) - IBIS Model
Package Pins Download
SOIC (D) 14 View options
SOT-23-THIN (DYY) 14 View options
TSSOP (PW) 14 View options
WQFN (BQA) 14 View options

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