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Product details

Parameters

Technology Family HCT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 6 IOL (Max) (mA) 4 IOH (Max) (mA) -4 ICC (Max) (uA) 20 Input type Schmitt-Trigger, TTL-Compatible CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Data rate (Mbps) 50 Rating Catalog open-in-new Find other Inverting buffer/driver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 open-in-new Find other Inverting buffer/driver

Features

  • Operating Voltage Range of 4.5 V to 5.5 V
  • Outputs Can Drive Up to 10 LSTTL Loads
  • Low Power Consumption: 20-µA Maximum ICC
  • Typical tpd = 18 ns
  • ±4-mA Output Drive at 5 V
  • Maximum Low Input Current of 1 µA Maximum
  • Inputs Are TTL-Voltage Compatible
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Description

The SNx4HCT14 devices contain six independent inverters. The devices perform the Boolean function Y = A in positive logic.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SNx4HCT14 Hex Schmitt-Trigger Inverters datasheet (Rev. G) Nov. 29, 2016
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Understanding Schmitt Triggers Sep. 21, 2011
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCEM662.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options

Ordering & quality

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